Todai Entrance Exam: Subject 2018 – Problem 2

(1) Thanks to this slide Circuit, State Diagram, State Table.

C achieves state i if the remainder obtained by dividing the sum of input values up to that time by 4 is i.

(2)

The states can be held in a 2-bit register. Their corresponding representation in 2-bit is:

  • State 0: 00.
  • State 1: 01.
  • State 2: 10.
  • State 3: 11.
I_{1}I_{0}S_{1}S_{0}S'_{1}S'_{0}
000000
011100
101000
110100
000101
010001
101101
111001
001010
010110
100010
111110
001111
011011
100111
110011

(3) Thanks to my labmate: “Carnot” in the Japanese version is “カルノー図”, which is in fact “Karnaugh”.

Thanks to Wikipedia:

Karnaugh diagram of S'_{1}:

S_{1}S_{0} \ I_{1}I_{0} 00011110
000011
010101
111010
101100

    \[ S'_{1} = I_{1}\bar{S_{1}}\bar_{S_{0}} + I_{1}\bar{I_{0}}\bar{S_{1}} + \bar{I_{1}}I_{0}\bar{S_{1}}S_{0} +I_{1}I_{0}S_{1}S_{0} + \bar{I_{1}}S_{1}\bar{S_{0}} + \bar{I_{1}}\bar{I_{0}}S_{1} \]

Karnaugh diagram of S'_{0}:

S_{1}S_{0} \ I_{1}I_{0}00011110
000110
011001
111001
100110

    \[ S'_{0} = I_{0}\bar{S_{1}}\bar{S_{0}} + \bar{I_{1}}\bar{I_{0}}S_{0} + I_{1}\bar{I_{0}}S_{0} + I_{0}S_{1}\bar{S_{0}} \]

(4) Will learn principles to draw logic gates diagrams later (maybe not). This one truly requires goddamn talent.


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