Todai Entrance Exam: Subject 2017 – Problem 2
Reference: Page 24 and Page 51 of Computer System Architecture (3rd Edition) by M. Morris R. Mano.
(1)
Asynchronous counter (see clock ripple)
(2)
Synchronous counter (pay attention to AND gates)
(3) Reference: Page 11 and Page 30 of Computer System Architecture (3rd Edition) by M. Morris R. Mano. Larger 5 & 6-variable Karnaugh Maps.
If we omit the input 
of the book, the K-map can be reduced by half.
![\[ \begin{Bmatrix} J_{Q_{0}} = 1 & K_{Q_{0}} = 1 \\ J_{Q_{1}} = Q_{0}\bar{Q_{3}} & K_{Q_{1}} = Q_{0} \\ J_{Q_{2}} = Q_{0}Q_{1} & K_{Q_{2}} = Q_{0}Q_{1} \\ J_{Q_{3}} = Q_{0}Q_{1}Q_{2} & K_{Q_{3}} = Q_{0} \end{matrix} \]](http://www.vynguyen.net/wp-content/ql-cache/quicklatex.com-8d03a0fa8cc1d5c8c09c6a50e4f61041_l3.png "Rendered by QuickLaTeX.com")
(4)Reference: Decade 4-bit Synchronous Counter in (2).
It turns out to be a series of JK flip-flops similar to (2) with 3 additional AND gates.
(5) Reference: Synchronous 3-bit Up/Down Counter.
Let the control signal be 
and 
be the replacement of 
.
![\[ Q_{\text{new}} = Q'D + QD' \]](http://www.vynguyen.net/wp-content/ql-cache/quicklatex.com-dc7e9f0ebfcb9d3b67f7d2a18b199832_l3.png "Rendered by QuickLaTeX.com")
