Todai Entrance Exam: Subject 2013 – Problem 2
(1) “A sequential circuit is an interconnection of flip-flops and gates.”. Reference: Page 28 of Computer System Architecture (3rd Edition) by M. Morris R. Mano.
(2) Reference: MOD Counters and Subject 2017 – Problem 2. It seems like a mod- counter is a counter with
flip-flops. And it seems to me that D-flip-flops cannot be used to construct a synchronous counter. So why did they mention D flip flop?
The solution to this question is the same as the solution to Problem 2.2 of Subject 2017.
(3) Quick K-map approach (not verified):
(In fact, they should have been respectively)
Previously, (note that
is out of the considered range):
00 | 01 | 11 | 10 | |
0 | 1 | |||
1 | x |
Now we get:
00 | 01 | 11 | 10 | |
0 | 1 | |||
1 | 1 | x |
Based on this, .
Previously (note that
and
is out of the considered range):
00 | 01 | 11 | 10 | |
0 | 1 | 1 | ||
1 | x | x |
Now we get:
00 | 01 | 11 | 10 | |
0 | 1 | 1 | ||
1 | 0 | x | x |
Based on this, .
Same goes for .
(4) Let runs from
to
. By K-map, we get:





