Todai Entrance Exam: Subject 2013 – Problem 2

(1) “A sequential circuit is an interconnection of flip-flops and gates.”. Reference: Page 28 of Computer System Architecture (3rd Edition) by M. Morris R. Mano.

(2) Reference: MOD Counters and Subject 2017 – Problem 2. It seems like a mod-2^{n} counter is a counter with n + 1 flip-flops. And it seems to me that D-flip-flops cannot be used to construct a synchronous counter. So why did they mention D flip flop?

The solution to this question is the same as the solution to Problem 2.2 of Subject 2017.

(3) Quick K-map approach (not verified):

    \[ 100 \rightarrow 000 : J_{Q_{2}} = K_{Q_{2}} = 1, J_{Q_{1}} = K_{Q_{1}} = 0, J_{Q_{0}} = K_{Q_{0}} = 0 \]

(In fact, they should have been (x, 1), (0, x), (x, 1) respectively)

Previously, J_{Q_{2}} = K_{Q_{2}} = Q_{1}Q_{0} (note that 111 is out of the considered range):

00011110
01
1x

Now we get:

00011110
01
11x

Based on this, J_{Q_{2}} = K_{Q_{2}} = Q_{1}Q_{0} + Q_{2}\bar{Q_{0}}\bar{Q_{1}}.

Previously J_{Q_{1}} = K_{Q_{1}} = Q_{0} (note that 101 and 111 is out of the considered range):

00011110
011
1xx

Now we get:

00011110
011
10xx

Based on this, J_{Q_{1}} = K_{Q_{1}} = Q_{0}.

Same goes for J_{Q_{0}} = K_{Q_{0}} = \bar{Q_{2}}.

(4) Let D_{2}D_{1}D_{0} runs from 110 to 101. By K-map, we get:

D_{2} = \bar{Q_{1}}\bar{Q_{0}}, D_{1} = \bar{Q_{0}}\bar{Q_{1}}\bar{Q_{2}} + Q_{0}Q_{1}, D_{0} = Q_{2} + Q_{0}\bar{Q_{1}}


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